1. Field of the Invention
The present invention relates to a semiconductor device including a through electrode and a manufacturing method thereof.
2. Description of the Related Art
In the past, a semiconductor device, such as a chip size package (CSP) semiconductor device or a system-in-package (SiP) semiconductor device, using a through electrode to achieve high integration and miniaturization of the semiconductor device was proposed. The following document discloses an example of a multi-layer package wherein a plurality of semiconductor chips having semiconductor circuits loaded thereon are mounted at high density, an SiP technology is used to configure a high-performance system within a short period of time, and the semiconductor chips are stacked three-dimensionally, thereby accomplishing dramatic downsizing of the semiconductor device.
Patent document 1: Japanese Patent Application Kokai (Laid-Open) No. 2007-53149
Patent document 1 discloses a method of achieving electric connection between the stacked semiconductor chips including forming a through electrode in a semiconductor substrate, which is a base member of each semiconductor chip, forming an electrode pad on the face opposite to a face where an integrated circuit is formed, and connecting the electrode pads of the respective semiconductor chips via the through electrode.
In particular, as shown in FIGS. 4 to 6 of Patent document 1, an interlayer insulation film and an element face electrode are formed on the semiconductor substrate, a mortar-shaped or funnel-shaped hole for the through electrode is formed in the semiconductor substrate until the hole reaches the interlayer insulation film from the side opposite to the element face, an insulation film is formed in the mortar-shaped hole, and a smaller hole is formed in the insulation film to expose the surface of the element face electrode. A film-shaped contact electrode is provided on the wall of the mortar-shaped hole, and the contact electrode is electrically connected to the element face electrode via the smaller hole. A bump is press-fit in the mortar-shaped hole via the contact electrode, and the stacked semiconductor chips are electrically connected to one another via the bump. Since the bump is inserted into the mortar-shaped hole, this configuration has an advantage that the bump can be mounted easily and accurately.
In the conventional technology disclosed in Patent document 1, however, if a semiconductor chip having a through electrode is used without a press-fit bump, the contact electrode and the element face electrode are electrically connected to each other via the small hole without the pressure-contact force from the bump. As a result, the contact area between the contact electrode and the element face electrode is decreased, and therefore, connection reliability is deteriorated. For this reason, the use of the disclosed technology Is limited to a structure in which the contact electrode and the element face electrode are brought into contact with each other under the pressure from the bump. This is disadvantageous and inconvenient.